1. Field of the Invention
The present invention relates to access of a shared memory by at least two controllers having different bus widths. The invention relates particularly but not exclusively to access of such a shared memory in a digital set-top-box of a digital television receiver.
2. Description of the Related Art
In digital television systems, a television is provided with a set-top-box to receive and decode a broadcast digital data stream which contains programme information for display on the television. The broadcast digital data stream may arrive at the set-top-box via a satellite or cable system, via a digital terrestrial system, or via a disk or tape. A disk or tape, such as a CD ROM drive in a personal computer, may provide digital video information for display on a monitor.
There are various known standards for digital video broadcasting (DVB) and one now commonly used standard is the MPEG-2 standard.
In the MPEG-2 DVB standard data is encoded into transport packets. Each transport packet is defined by the standard as consisting of 188 bytes, comprising 4 header bytes and 184 payload bytes (xe2x80x9cthe data payloadxe2x80x9d). For transmission, the transport packets are time division multiplexed into a transport stream. At the receiver in the set-top-box, the transport stream is demultiplexed to recover the transport packets. Optionally the transport packets may be scrambled and encoded with error correction information for transmission, and then descrambled and error-checked at the receiver.
The data payload in the transport packets is, according to the MPEG-2 standard, one of two types. The first type is known as a packetised elementary stream (PES), and the second type is known as program specific information (PSI).
The packetised elementary streams (PESs) form the video, audio and private data information of the broadcast. A PES packet may contain all sorts of data, audio or video, and also other information such as teletext or other user-defined general data. The MPEG-2 transport stream is made up of one or more PESs (either video, audio or private). The MPEG-2 transport stream is primarily intended for the transport of TV programmes over long distances. This type of stream can combine, in the same multiplex, many programmes each of them being composed of one or more PESs. In order that the receiver can cope with this mix of programme information, the MPEG-2 standard defines four types of tables, which together make up the MPEG-2 program specific information (PSI).
At each decoder or set-top-box, the transport stream is decoded. To achieve the decoding of the transport stream, each set-top-box is provided with a transport interface, which provides an interface between the transport stream input to the box and the actual MPEG-2 decoders which decode the audio and video information and sections broadcasts.
The transport interface demultiplexes the transport stream to retain only those transport packets which are required by the particular set-top-box for decoding. The transport stream is a set of different services time division multiplexed, and the purpose of the transport interface is to demultiplex them. At a front input end of the transport interface, a time demultiplex function is performed to separate the transport stream into its component transport packets.
Each transport packet has associated therewith in its header a packet identifier (PID) which identifies the type of packet and various information associated with the data in the packets including the type of packet (PES or PSI). Each particular receiver or set-top-box is only interested in receiving packets having packet identifiers of interest to the particular set-top-box, for instance those associated with a particular television programme selected for viewing. Thus once the incoming transport stream has been time demultiplexed to recover the transport packets, it is necessary to further demultiplex the transport packets to retain only those having packet identifiers required by the receiver.
The transport interface merely uses the header of PES transport packets to demultiplex them, and stores the data payload of the demultiplexed packets in the memory. The transport interface similarly demultiplexes PSI transport packets, but then filters the sections of the demultiplexed packets to retain only sections required by the receiver, before storing the filtered sections in the memory without any further processing.
Although the MPEG-2 DVB standard is one of the main digital video broadcast standards, there are variations within the standard. It is desirable to provide receivers having decoders which are generally as flexible as possible not only to cope with variations in the standard but, if necessary, to enable the receiver to be used with a different standard.
It is therefore generally desirable to provide a single receiver which provides the flexibility of enabling different types of digital video broadcast standards to be used by utilising a programmable transport interface. Utilising such a receiver in a set-top-box may enable the set-top-box to be switched between two or more types of syntax format associated with different standards in situ.
Such a programmable transport interface requires a transport processor to be provided in addition to a main processor of the receiver in the set-top-box. Flexibility in the programmable transport interface is provided by a transport memory the contents of which can be altered under the control of the main processor during configuration, and which can be accessed by the transport processor and main processor during normal operation.
Where there is a requirement for such shared memory access, it is quite common for the wordlengths or bus widths of the two processors to be different. In such cases the memory wordlength or bus access width will be compatible with one of the processor wordlengths, but not the other.
In a programmable transport interface for use in a digital-set-top box, it is usual for the transport controller, which is required to perform less complex processing operations, to have a smaller wordlength than that of the main processor. The memory is chosen to have a wordlength directly compatible with the transport controller, since the transport controller performs the majority of memory accesses to the memory.
There is therefore a need for arbitration between the two processors to overcome problems caused by the different wordlength access. The most common problem arises because the processor having the longer wordlength must always access the memory in its own wordlength. Therefore if such processor has a wordlength of twice that of the memory, it will always read or write two memory words even if a single memory word access is required. It is therefore a problem that, without proper arbitration, such processor may corrupt an adjacent memory word or make it invalid whilst writing a valid memory word.
It is therefore an object of the present invention to provide a simple arbitration scheme for access to a shared memory by at least two control circuits having different wordlengths which does not unduly complicate the circuitry associated with the memory.
The present invention thus provides a method of controlling first and second memory accesses to a shared memory arranged to store blocks of data, comprising the steps of arbitrating between first and second memory accesses, accessing a block of data responsive to each first memory access, accessing two blocks of data responsive to each second memory access, wherein each second memory write access comprises reading blocks of data from first and second memory locations and writing blocks of data to first and second memory locations.
The invention also provides circuitry for accessing a memory in which data is stored as blocks, comprising arbitration circuitry for controlling access to the memory, first memory access circuitry connected to the arbitration circuitry for accessing a stored data block, second memory access circuitry connected to the arbitration circuitry for accessing two stored data blocks, wherein on a write access the second memory access circuitry reads data blocks from first and second memory locations and writes two data blocks, to the first and second memory locations.
The invention will now be described with reference to the accompanying drawings.